1. Field of Use
This invention relates to address transfer apparatus and more particularly to methods and apparatus for veryifying that address information is being transferred without error.
2. Prior Art
In general, many data processing systems do not include apparatus which check address transfers, particularly when the address being transferred is used to access a memory device. To ensure that memory addressing proceeded properly in such instances, one prior art approach was to combine the parity bits of the address applied to the memory device with the address of the data and store the resulting information in the addressed location.
During a subsequent cycle, the stored resulting bit was used to signal the presence of an error or fault condition associated with the location being accessed. An example of such an arrangement is described in U.S. Pat. No. 3,789,204 titled, "Self-Checking Digital Storage System", invented by George J. Barlow.
While the above arrangement was effective in detecting memory faults or errors, it only detected indirectly errors occurring during the transfer of the address. The verification of such transfers becomes particularly important where address being transferred passes through an incrementing circuit. In this type of arrangement, it becomes difficult to ensure that the resulting address is valid without adding a substantial amount of circuit redundancy. That is, a common approach has been to provide two address incrementing circuits and a comparator. The comparator by comparing the incremental addresses generated by both incrementing circuits is able to verify that the incrementing operation took place without error. Thereafter, new parity can be generated for the verified incremented address.
In addition to the added duplication, the above approach increases substantially, the amount of time required for verifying that the address transfer proceeded without error. In today's high speed data processing systems, the introduction of this type of address verification can substantially reduce system performance. This problem is further compounded where the addresses being transferred have undergone a virtual to physical address translation operation which involved the generation of parity bits further delaying the transfer of the address to the memory device such as a cache memory. In such arrangements, disparities in time between the availability of the generated parity bits associated with the physical address and the normal availability of physical address further adversely affects system performance resulting in more stringent requirements being placed on the virtual memory management unit which performs such address translations.
Accordingly, it is a primary object of the present invention to provide an improved method and apparatus for transferring addresses and their associated integrity bits through an address path which includes an incrementing circuit.
It is a further, more specific object of the present invention to provide an improved method and apparatus which verifies if the transfer of addresses proceeded without error.